1. Field of the Invention
This invention pertains in general to a non-volatile memory device and, more particularly, to a non-volatile memory device with field-enhancing floating gate and a method for forming the same.
2. Description of the Related Art
A non-volatile memory device may be programmed through Fowler-Nordheim tunneling or "hot" electron injection. Hot electrons are those with high kinetic energy and may be acquired through a locally-enhanced electric field. Some electrons in the channel region of the device substrate may be induced through either Fowler-Nordheim tunneling or hot electron injection to penetrate a dielectric layer that separates the substrate from a floating gate. When the electrons have penetrated the dielectric layer and stored at the floating gate, the device is said to be programmed. The stored electrons may be removed from the floating gate through a control gate, or select gate, that overlaps the floating gate. The floating gate and the control gate are separated by a second dielectric layer. With Fowler-Nordheim tunneling, the electrons stored in the floating gate may be induced to tunnel through the second dielectric layer to the control gate. After the stored electrons are removed from the floating gate, the device is said to be erased.
U.S. Pat. No. 5,278,087 ("the '087 patent") discloses a method of making a single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate. U.S. Pat. No. 5,242,848 ("the '848 patent") discloses a self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device.
FIG. 1 is a cross-sectional side view of a single transistor non-volatile electrically alterable memory cell disclosed in the '087 and the '848 patents. Referring to FIG. 1, a memory cell 10 includes a semiconductor substrate 12. Substrate 12 includes a drain region 16, a source region 14 and a channel region 18 therebetween. Disposed over substrate 12 is a first layer 20 of dielectric material, which may be composed of silicon dioxide, silicon nitride, or silicon oxynitride. A polysilicon floating gate 22 is disposed over first layer 20 and overlaps a portion of channel region 18 and a portion of source region 14. A second dielectric layer 25 has a first section 24 disposed over floating gate 22 and a second section 26 adjacent to floating gate 22. Layer 25 may be composed of silicon dioxide, silicon nitride, or silicon oxynitride.
Cell 10 also includes a control gate 29 having a first portion 28 and a second portion 30. First portion 28 is disposed over first portion 24 of layer 25 and second portion 30 is disposed over layer 20 and contiguous with second portion 26 of layer 25. Second portion 30 also extends over a portion of drain region 16 and a portion of channel region 18.
Both the '087 and the '848 patents describe that cell 10 may be programmed by applying a ground potential to drain region 16, a threshold voltage to control gate 29, and a positive high voltage on the order of 12 volts to source region 14. Under such a bias condition, electrons from drain region 16 flow towards source region 14 through channel region 18. A locally generated electrical field in channel region 18 causes some of the electrons to become "hot", i.e., acquire kinetic energy. For those having acquired enough kinetic energy, some will inject into floating gate 22 through layer 20.
The '087 and '848 patents also describe that the electrons stored in floating gate 22 after programming may be removed through Fowler-Nordheim tunneling. By applying 15 volts to control gate 29 and a ground potential to source region 14 and drain region 16, the stored electrons will tunnel through layer 25 to control gate 29 and may be removed through control gate 29. Electron tunneling is attributed to a locally enhanced field from floating gate 22.
The '087 and the '848 patents are hereby incorporated by reference.